Measuring and Navigating the Gap Between FPGAs and ASICs

Measuring and Navigating the Gap Between FPGAs and ASICs Ian Carlos Kuon Doctor of Philosophy Graduate Department of Electrical and Computer Engineering University of Toronto 2008 Field-programmable gate arrays (FPGAs) have enjoyed increasing use due to their low non-recurring engineering (NRE) costs and their straightforward implementation process. However, it is recognized that they have higher per unit costs, poorer performance and increased power consumption compared to custom alternatives, such as applicationspecific integrated circuits (ASICs). This thesis investigates the extent of this gap and it examines the trade-offs that can be made to narrow it. The gap between 90 nm FPGAs and ASICs was measured for many benchmark circuits. For circuits that only make use of general-purpose combinational logic and flipflops, the FPGA-based implementation requires 35 times more area on average than an equivalent ASIC. Modern FPGAs also contain “hard” specific-purpose circuits such as multipliers and memories and these blocks are found to narrow the average gap to 18 for our benchmarks or, potentially, as low as 4.7 when the hard blocks are heavily used. The FPGA was found to be on average between 3.4 and 4.6 times slower than an ASIC and this gap was not influenced significantly by hard memories and multipliers. The dynamic power consumption is approximately 14 times greater on average on the FPGA than on the ASIC but hard blocks showed promise for reducing this gap. This is one of the most comprehensive analyses of the gap performed to date. The thesis then focuses on exploring the area and delay trade-offs possible through architecture, circuit structure and transistor sizing. These trade-offs can be used to selectively narrow the FPGA to ASIC gap but past explorations have been limited in